Sistem Komputer: Perspektif Seorang Pemrogram (Edisi Global): Perbandingan Arsitektur Hardware: SRAM vs. DRAM

Dasar Hierarki

Hierarki memori bergantung pada kompromi antara RAM Statis (SRAM) dan RAM Dinamis (DRAM). SRAM menggunakan sel memori bistabil dengan 6 transistor sel memori bistabil. Bayangkan sebuah bandul terbalik: ia stabil di dua posisi tetapi metastabil di tengah. Kestabilan bistabil ini membuatnya cepat, mahal, dan tidak sensitif terhadap gangguan. DRAM, sebaliknya, menyimpan bit sebagai muatan dalam kapasitor kecil (sekitar 30 × 10⁻¹⁵ farad). Karena muatan bocor, DRAM lebih lambat dan membutuhkan pembaruan terus-menerus.

Organisasi DRAM & Transaksi Bus

Untuk meminimalkan jumlah pin, bit DRAM dibagi menjadi $d$ super sel dalam kisi $r \times c$ di mana $rc=d$. Mengakses data membutuhkan proses dua langkah: pengendali Pengendali Memori mengirimkan RAS (Penggerak Akses Baris), memindahkan baris ke buffer baris, diikuti oleh CAS (Penggerak Akses Kolom). Ini menjelaskan mengapa sumarraycols secara inheren lebih lambat: karena sering gagal mengakses buffer baris.

Pergerakan Data

Data bergerak melalui transaksi bus melintasi Bus Sistem dan Bus Memori, yang dihubungkan oleh jembatan I/O. Instruksi movq A, %rax instruksi (Transaksi Baca) memicu jembatan untuk menerjemahkan permintaan CPU menjadi sinyal kisi DRAM.

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QUESTION 1

Which physical characteristic explains why SRAM is faster but less dense than DRAM?

SRAM uses capacitors that require periodic refreshing.

SRAM uses a 6-transistor bistable cell, while DRAM uses a single transistor and capacitor.

DRAM uses the inverted pendulum principle for stability.

SRAM requires RAS/CAS strobing for every bit access.

QUESTION 2

In a 128 x 8 DRAM, why does the controller send the Row Address (RAS) and Column Address (CAS) separately?

To increase the power consumption defined by P = fCV².

To allow the CPU to perform polynomial evaluation in between.

To reduce the number of address pins required on the chip by minimizing max(br, bc).

To ensure the firmware can intercept the memory bus transaction.

QUESTION 3

Identify the sequence for a 'Read transaction' of 'movq A, %rax'.

CPU places address on System Bus -> I/O Bridge translates to Memory Bus -> DRAM returns data to CPU.

DRAM sends data to System Bus -> I/O Bridge sends to Register file.

CPU places data on Memory Bus -> Bridge translates to System Bus -> Address A is updated.

QUESTION 4

Match the address partitioning component: CI

The cache block offset

The cache set index

The cache tag

The DRAM supercell width

QUESTION 5

What would the hit rate be if the cache were twice as big for a grid array scan problem with a 64 B block size?

It would double exactly.

It depends on spatial locality; for a stride-1 scan, it remains (BlockSize - sizeof(type)) / BlockSize.

It would become 100% because of compulsory misses.

It would decrease because of conflict misses.